A CVD technique is a film forming method that is widely employed in the process of manufacturing a semiconductor device.
In today's ultrahigh speed semiconductor devices, a gate length can be as short as 0.1 μm or less thanks to the advancement in the miniaturization technique. Generally, the operational speed of a semiconductor device improves with the miniaturization. However, the film thickness of a gate insulating film needs to be reduced in accordance with a scaling rule in such an extremely miniaturized semiconductor device because miniaturization inevitably requires a reduction in the gate length.
Similarly, the film thickness of a capacitor insulating film needs to be decreased to a few nanometers or less in order to secure a sufficient capacitance in a semiconductor device having a super miniaturized capacitor, e.g., DRAM.
Therefore, efforts have been made to find a method for forming a gate insulating film or a capacitor insulating film with a high-k dielectric material, e.g., HfO2 or ZrO2, which allows a reduction in the electrical film thickness while maintaining its large physical thickness to thereby avoid an increase in the tunneling current.
Conventionally, such a high-k dielectric film has been made through a MOCVD technique using a metal organic (MO) material which can be deposited at a low temperature, e.g., at a temperature not exceeding 600° C. (see Japanese Patent Laid-open Application No. H9-129626).
However, the high-k dielectric film formed through the MOCVD method has an average roughness Ra of a few Å exceeding, e.g., 0.3 nm in general. If such a high-k dielectric film is employed as the aforementioned gate insulting film in an ultrahigh speed transistor or as the capacitor insulting film in a super miniaturized DRAM, several problems may arise: namely, a tunneling leakage current path may form locally at a thin part of the film; a concentration of an electric field may occur due to an irregularity on the film surface; and the tunneling leakage current may increase in a local leakage current path.
For instance, in case of a HfO2 film formation in which tetra(tert-butoxy)hafnium is employed as a raw material, the average roughness Ra of the film is about 0.45 nm when the substrate is maintained at 550° C. and processed under a pressure of 0.3 Torr.
On the other hand, the average roughness Ra of a gate insulating film for MISFET is required to be smaller than or equal to 0.2 nm when the gate length thereof is 0.1 μm or less.